1. Field of the Invention
The present invention relates to a method for fabricating semiconductor devices, and more particularly to a method for forming impurity junction regions of a semiconductor device, capable of forming impurity junction regions with a small depth by selectively forming defecting regions and amorphous regions in a semiconductor substrate, thereby achieving an improvement in the characteristics of the semiconductor device.
2. Description of the Prior Art
Where N.sup.+ P junctions are formed in impurity junction regions of a semiconductor device, it is possible to reduce the depth of the junctions because the N.sup.+ P junctions have a large mass, a small ion implantation width and a low diffusion coefficient. In order to form such N.sup.+ P junctions, BF.sub.2 ions are typically implanted in a semiconductor substrate. In this case, however, it is difficult to form thin junctions because of a severe channeling phenomenon caused by boron ions and a high diffusion coefficient of boron.
Furthermore, a straggling phenomenon that implanted ions are laterally straggled occurs at the ion implanting step. Due to such a straggling phenomenon, boron ions penetrate portions of the semiconductor substrate disposed beneath end portions of the gate oxide film and insulating film spacers formed on the side walls of the gate electrode.
Since the boron ions penetrating the semiconductor substrate portions beneath the insulating film spacers have a high diffusion coefficient, they are laterally diffused, thereby reducing the effective electrode length, namely, the channel length.
Due to the reduced channel length of the semiconductor device, a short channel effect occurs. That is, the current between the source and drain increases continuously without being saturated even when the drain voltage passes its pinch-off point and reaches its saturated point. Also, a punch-through phenomenon occurs.
Fluorine ions contained in BF.sub.2 implanted in the semiconductor substrate as impurity ions for impurity junction regions serve to form a thin amorphous layer. Along with primary defects formed at the ion implanting step, the thin amorphous layer serves to form an extended defect in the surface portion of the semiconductor substrate at a subsequent annealing step. As a result, an increase in contact resistance occurs at a step of forming contacts.
Such undesirable phenomenons result in a degradation in the characteristics of the semiconductor device such as an increase in the amount of junction leakage current. Consequently, there are problems such as a degradation in reliability and difficulty in integration.
Conventional methods involving the above-mentioned problems will be described in detail, in conjunction with FIGS. 1 and 2.
FIG. 1 is a sectional view of a semiconductor device, explaining a conventional method for forming impurity junction regions.
In accordance with this method, a semiconductor substrate 1 is first prepared, which is provided with an N well 2, as shown in FIG. 1. The N well 2 is formed in the surface portion of the semiconductor substrate 1. An element-isolating oxide film 3 is then formed on a desired portion of the semiconductor substrate 1 using a LOCOS process. The element-isolating oxide film 3 serves to define active and field regions of the semiconductor substrate 1. Thereafter, a gate oxide film 4 is formed on a portion of the semiconductor substrate 1 corresponding to the active region. On the gate oxide film 4, a gate electrode 5 is formed.
Subsequently, insulating film spacers 6 are formed on opposite side walls of the gate oxide film 4 and gate electrode 5, respectively.
Using the upper surface of the gate electrode 5, the insulating film spacers 6 and the element-isolating oxide film 3 as a mask, BF.sub.2 impurity ions are implanted in the active region of the semiconductor substrate 1, thereby forming impurity junction regions 7.
In accordance with the above-mentioned conventional method, however, an extended defect 8 with a width of "a" is formed in each impurity junction region 7 at the surface portion of the semiconductor substrate 1, as shown in FIG. 1. This will be described in more detail.
Since this method uses BF.sub.2 as impurity ions for impurity junction regions, it involves a short channel effect and a punch-through phenomenon. This is because BF.sub.2 impurity ions are laterally straggled due to a high diffusion coefficient of boron (B) contained in BF.sub.2.
As a result, a thin amorphous layer is formed at each impurity junction region by fluorine (F) contained in BF.sub.2. Along with the primary defect occurring at the ion implanting step, the thin amorphous layer serves to form an extended defect in the surface portion of the semiconductor substrate where the N well is disposed, namely, the substrate surface portion disposed beneath the insulating spacers and element-isolating oxide film, at a subsequent annealing step.
Referring to FIG. 2, another conventional method for forming impurity junction regions is illustrated. FIG. 2 is a sectional view of a semiconductor device formed with impurity junction regions in accordance with this method.
In accordance with the conventional method, a semiconductor substrate 1 is first prepared, which is provided with an N well 12, as shown in FIG. 2. The N well 12 is formed in the surface portion of the semiconductor substrate 11. An element-isolating oxide film 13 is then formed on a desired portion of the semiconductor substrate 11 using a LOCOS process. The element-isolating oxide film 13 serves to define active and field regions of the semiconductor substrate 11. Thereafter, a gate oxide film 14 is formed on a portion of the semiconductor substrate 11 corresponding to the active region. On the gate oxide film 14, a gate electrode 15 is formed.
Subsequently, insulating film spacers 16 are formed on opposite side walls of the gate oxide film 14 and gate electrode 15, respectively.
Using the upper exposed surface of the gate electrode 15, the insulating film spacers 16 and the element-isolating oxide film 13 as a mask, impurity ions with a large molecular weight are implanted in the active region of the semiconductor substrate 11, thereby forming amorphous layers 17 respectively in desired surface portions of the semiconductor substrate 11.
BF.sub.2 impurity ions are then implanted in the active region of the semiconductor substrate 11, thereby forming impurity junction regions 18 beneath the amorphous layers 17. Each impurity junction region 18 has a small thickness by virtue of a suppressed channelling by boron ions.
In accordance with the above-mentioned conventional method, however, an extended defect 19 with a width of "b" is formed beneath the interface between each amorphous layer 17 and each corresponding impurity junction region 18 at a subsequent annealing step because the amorphous layer 17 is formed using impurity ions with a large molecular weight. Thus, the extended defect is widely distributed such that it extends to the end of the gate oxide film, thereby resulting in an increase in the amount of junction leakage current.